1. Field of the Invention
The present invention relates to the field of system organization of data processors and in particular relates to the field wherein a plurality of processors share a local bus to access and control a system bus and/or a private bus, and wherein this plurality of processors share resources for controlling the private and system buses. In configurations displaying both private and common buses, the plurality of processors on the local bus uses resources located on the private bus when it is not using resources located on the common bus. Traditionally, private bus resources have included instruction memory, non-intelligent peripherals such as latches and intelligent peripherals such as direct memory access devices, serial interface devices and peripheral controller processors.
2. Description of the Prior Art
As the cost of integrated circuit, semiconductor microprocessors continues to decrease and as their acceptance continues to increase, an accelerating number of applications are found wherein such microprocessors can be organized to intelligently perform a plurality of complex computing operations which cannot be performed by a single integrated circuit made by presently known technology. Thus, microprocessors which may have been previously dedicated to rather simple operations requiring a high number of simple repetitive steps are increasingly required to be adapted to applications wherein the complexity and intelligence required to perform the operations is much greater than can be accomplished by previously known methods and circuits.
Prior art and state of the art microprocessors are limited by process and packaging restrictions due to a limited manufacturable size of the semiconductor chip and package. The demand for increased computing capacity to perform complex operations has exceeded the present ability to provide sufficient circuitry within the size limitations of manufacturably practical and cost competitive microprocessors.
Therefore, various organizations wherein a plurality of microprocessors have been organized to share either a private bus or a system or common bus have been devised to distribute computing capacity among a plurality of modules. Common bus is taken to mean a bus which is shared by a plurality of processors which either execute unrelated tasks using shared resources (peripherals) or which execute a single task by partitioning the execution among the plurality of processors. Generally, in such prior art systems a single micro-processor, or direct memory access unit under control of the microprocessor, performs all the required operations with respect to a local bus and shares a system bus with other processors. In this manner, peripheral circuitry, which are shared resources which perform various ancillary functions, can be serviced over a single system bus with the required intelligence or computing capacity distributed among a plurality of single processor controlled local buses. Nevertheless, the demand for complex computing operations has continued to the point where prior art microprocessors which execute a single instruction stream cannot perform the needed local bus operations without having extended computing capacity.
What is described herein is an apparatus and methodology for cooperative and concurrent coprocessing which overcomes each of the shortcomings of the prior art.